MCP1727
( T J ( MAX ) – T A ( MAX ) )
R θ JA
The maximum power dissipation capability for a
package can be calculated given the junction-to-
ambient thermal resistance and the maximum ambient
temperature for the application. Equation 5-4 can be
used to determine the package maximum internal
power dissipation.
EQUATION 5-4:
P D ( MAX ) = ---------------------------------------------------
P D(MAX) = Maximum device power dissipation
T J(MAX) = maximum continuous junction
temperature
T A(MAX) = maximum ambient temperature
R θ JA = Thermal resistance from junction to
ambient
EQUATION 5-5:
T J ( RISE ) = P D ( MAX ) × R θ JA
T J(RISE) = Rise in device junction temperature
over the ambient temperature
P D(MAX) = Maximum device power dissipation
R θ JA = Thermal resistance from junction to
ambient
EQUATION 5-6:
T J = T J ( RISE ) + T A
T J = Junction temperature
T J(RISE) = Rise in device junction temperature
over the ambient temperature
T A = Ambient temperature
? 2007 Microchip Technology Inc.
5.3 Typical Application
Internal power dissipation, junction temperature rise,
junction temperature and maximum power dissipation
is calculated in the following example. The power
dissipation as a result of ground current is small
enough to be neglected.
5.3.1 POWER DISSIPATION EXAMPLE
Package
Package Type = 3x3DFN
Input Voltage
V IN = 3.3V ± 5%
LDO Output Voltage and Current
V OUT = 2.5V
I OUT = 1.5A
Maximum Ambient Temperature
T A(MAX) = 60°C
Internal Power Dissipation
P LDO(MAX) = (V IN(MAX) – V OUT(MIN) ) x I OUT(MAX)
P LDO = ((3.3V x 1.05) – (2.5V x 0.975))
x 1.5A
P LDO = 1.54 Watts
5.3.1.1 Device Junction Temperature Rise
The internal junction temperature rise is a function of
internal power dissipation and the thermal resistance
from junction-to-ambient for the application. The
thermal resistance from junction-to-ambient (R θ JA ) is
derived from an EIA/JEDEC standard for measuring
thermal resistance for small surface-mount packages.
The EIA/JEDEC specification is JESD51-7 “High
Effective Thermal Conductivity Test Board for Leaded
Surface-Mount Packages”. The standard describes the
test method and board specifications for measuring the
thermal resistance from junction to ambient. The actual
thermal resistance for a particular application can vary
depending on many factors such as copper area and
thickness. Refer to AN792, “A Method to Determine
How Much Power a SOT23 Can Dissipate in an
Application” (DS00792), for more information regarding
this subject.
T J(RISE) = P TOTAL x R θ JA
T JRISE = 1.54 W x 41.0 ° C/W
T JRISE = 63.14 ° C
DS21999B-page 21
相关PDF资料
MCP1754ST-5002E/MB IC REG LDO 5V .15A SOT89-3
MCP1791T-3302E/DC IC REG LDO 3.3V 70MA SOT223-5
MCP1801T-1202I/OT IC REG LDO 1.2V .15A SOT23-5
MCP1802T-1202I/OT IC REG LDO 1.2V .26A SOT23-5
MCP1804T-A002I/DB IC REG LDO 10V .15A SOT223-3
MCP1824ST-3002E/DB IC REG LDO 3V .3A SOT223-3
MCP1825T-3302E/DC IC REG LDO 3.3V .5A SOT223-5
MCP1826T-5002E/DC IC REG LDO 5V 1A SOT223-5
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